Optimal Repair Rate and Area Reduction for Embedded Memories by Using Bira & Amt

As the capacity and density of embedded memories have rapidly increased, the probability of memory faults will increase. That results in yield drops and quality degradation.Yield improvement of embedded memories have become very important.Yield refers to the percentage of good die on the wafer. For embedded memories Built-In-Redundancy-Analysis (BIRA)is used to achieve optimal repair rate and yield improvement. In this Project the proposed scheme generates set of test patterns with weights 0, 0.5 and 1 using an accumulator-based-3 weighttest pattern generation. In a Built-In Redundant analysis (BIRA) scheme, it performs exhaustive search to find and repair the faults in RAM. It uses part of spare memory as an AMT(Address Mapping Table) to reduce the faulty cell address to its logical address which consumes less area. And by using tiling technique in spare memory permanent faults were handled. These reduced addresses are stored in CAM (Content Addressable Memory) which is used during the Redundant Analysis procedure.